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Data Sheet No. PD60338
IRMCK312
Dual Channel Sensorless Motor Control IC for Appliances
Features
MCE (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Integrated Power Factor Correction control Supports both interior and surface permanent magnet motors Built-in hardware peripheral for single shunt current feedback reconstruction No external current or voltage sensing operational amplifier required Dual channel three/two-phase Space Vector PWM Three-channel analog output (PWM) Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Two serial communication interface (UART) I2C/SPI serial interface Watchdog timer with independent analog clock Three general purpose timers/counters Two special timers: periodic timer, capture timer Internal `One-Time Programmable' (OTP) memory and internal RAM for final production usage Pin compatible with IRMCF312 RAM version 1.8V/3.3V CMOS
TM
Product Summary
Maximum crystal frequency Maximum internal clock (SYSCLK) frequency Maximum 8051 clock frequency Sensorless control computation time MCE
TM
60 MHz 128 MHz 33 MHz 11 sec typ 16 bit signed 56K bytes 8K bytes 2 sec 16 bits/ SYSCLK 11 12 bits 2 sec 2 SYSCLK 8 bits 57.6K bps 36 QFP100 -40C ~ 85C
computation data range
8051 OTP Program memory MCE program and Data RAM GateKill latency (digital filtered) PWM carrier frequency counter A/D input channels A/D converter resolution A/D converter conversion speed 8051 instruction execution speed Analog output (PWM) resolution UART baud rate (typ) Number of I/O (max) Package (lead-free) Operating temperature
Description
IRMCK312 is a high performance OTP based motion control IC designed primarily for appliance applications. IRMCK312 is designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control. IRMCK312 contains two computation engines. One is Motion Control Engine (MCETM) for sensorless control of permanent magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one monolithic chip. The MCETM contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2cycle instruction execution (16MIPS at 33MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process signal monitoring and command input. An advanced graphic compiler for the MCETM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments. IRMCK312 comes with a small QFP100 pin lead-free package.
Rev 1.0
IRMCK312
TABLE OF CONTENTS
Overview...................................................................................................................................... 5 IRMCK312 Block Diagram and Main Functions........................................................................ 6 Pinout........................................................................................................................................... 8 Input/Output of IRMCK312 ........................................................................................................ 9 4.1 8051 Peripheral Interface Group......................................................................................... 10 4.2 Motion Peripheral Interface Group ..................................................................................... 11 4.3 Analog Interface Group ...................................................................................................... 11 4.4 Power Interface Group ........................................................................................................ 12 4.5 Test Interface....................................................................................................................... 12 5 Application Connections ........................................................................................................... 13 6 DC Characteristics ..................................................................................................................... 14 6.1 Absolute Maximum Ratings ............................................................................................... 14 6.2 System Clock Frequency and Power Consumption............................................................ 14 6.3 Digital I/O DC Characteristics............................................................................................ 15 6.4 PLL and Oscillator DC Characteristics............................................................................... 16 6.5 Analog I/O DC Characteristics ........................................................................................... 16 6.6 Under Voltage Lockout DC Characteristics ....................................................................... 17 6.7 AREF Characteristics.......................................................................................................... 17 7 AC Characteristics ..................................................................................................................... 18 7.1 PLL AC Characteristics ...................................................................................................... 18 7.2 Analog to Digital Converter AC Characteristics ................................................................ 19 7.3 Op Amp AC Characteristics ............................................................................................... 19 7.4 SYNC to SVPWM and A/D Conversion AC Timing......................................................... 20 7.5 GATEKILL to SVPWM AC Timing.................................................................................. 21 7.6 Interrupt AC Timing ........................................................................................................... 21 7.7 I2C AC Timing .................................................................................................................... 22 7.8 SPI AC Timing.................................................................................................................... 23 7.8.1 SPI Write AC timing .................................................................................................... 23 7.8.2 SPI Read AC Timing.................................................................................................... 24 7.9 UART AC Timing .............................................................................................................. 25 7.10 CAPTURE Input AC Timing .......................................................................................... 26 7.11 JTAG AC Timing ............................................................................................................ 27 7.12 OTP Programming Timing .............................................................................................. 28 8 I/O Structure .............................................................................................................................. 29 9 Pin List....................................................................................................................................... 32 10 Package Dimensions............................................................................................................... 36 11 Part Marking Information....................................................................................................... 37 12 Ordering Information ............................................................................................................. 37 1 2 3 4
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IRMCK312
TABLE OF FIGURES
Figure 1. Typical Application Block Diagram Using IRMCK312 ................................................. 5 Figure 2. IRMCK312 Internal Block Diagram ............................................................................... 6 Figure 3. IRMCK312 Pin Configuration......................................................................................... 8 Figure 4. Input/Output of IRMCK312 ............................................................................................ 9 Figure 5. Application Connection of IRMCK312......................................................................... 13 Figure 6. Clock Frequency vs. Power Consumption..................................................................... 14 Figure 7 Crystal oscillator circuit.................................................................................................. 18 Figure 8 Voltage droop of sample and hold .................................................................................. 19 Figure 9 SYNC to SVPWM and A/D conversion AC Timing...................................................... 20 Figure 10 GATEKILL to SVPWM AC Timing............................................................................... 21 Figure 11 Interrupt AC Timing ..................................................................................................... 21 Figure 12 I2C AC Timing.............................................................................................................. 22 Figure 13 SPI AC Timing ............................................................................................................. 23 Figure 14 SPI Read AC Timing .................................................................................................... 24 Figure 15 UART AC Timing ........................................................................................................ 25 Figure 16 CAPTURE Input AC Timing........................................................................................ 26 Figure 17 JTAG AC Timing ......................................................................................................... 27 Figure 18 OTP Programming Timing ........................................................................................... 28 Figure 19 All digital I/O except motor PWM output ....................................................................... 29 Figure 20 RESET, GATEKILL I/O ................................................................................................. 29 Figure 21 Analog input..................................................................................................................... 30 Figure 22 Analog operational amplifier output and AREF I/O structure ..................................... 30 Figure 23 VPP programming pin I/O structure .................................................................... 30 Figure 24 VSS and AVSS pin structure ........................................................................................... 31 Figure 25 VDD1 and VDDCAP pin structure.................................................................................. 31 Figure 26 XTAL0/XTAL1 pins structure ..................................................................................... 31
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IRMCK312
TABLE OF TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Absolute Maximum Ratings............................................................................................ 14 System Clock Frequency................................................................................................. 14 Digital I/O DC Characteristics ........................................................................................ 15 PLL DC Characteristics .................................................................................................. 16 Analog I/O DC Characteristics ....................................................................................... 16 UVcc DC Characteristics ................................................................................................ 17 AREF DC Characteristics ............................................................................................... 17 PLL AC Characteristics .................................................................................................. 18 A/D Converter AC Characteristics.................................................................................. 19 Current Sensing OP Amp AC Characteristics............................................................... 19 SYNC AC Characteristics............................................................................................. 20 GATEKILL to SVPWM AC Timing ............................................................................ 21 Interrupt AC Timing...................................................................................................... 21 I2C AC Timing .............................................................................................................. 22 SPI Write AC Timing.................................................................................................... 23 SPI Read AC Timing..................................................................................................... 24 UART AC Timing......................................................................................................... 25 CAPTURE AC Timing ................................................................................................. 26 JTAG AC Timing.......................................................................................................... 27 OTP Programming Timing............................................................................................ 28 Pin List .......................................................................................................................... 35
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IRMCK312 1 Overview
IRMCK312 is a new International Rectifier integrated circuit device primarily designed as a onechip solution for complete inverter controlled appliance dual motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK312 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCETM) for permanent magnet motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCK312 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. The sensorless control is the same for both motors with a single shunt current sensing capability. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using IRMCK312. IRMCK312 is intended for volume production purpose and contains 64K bytes of OTP (One Time Programming) ROM, which can be programmed through a JTAG port. For a development purpose use, IRMCF312 contains a 48k byte of RAM in place of program OTP to facilitate an application development work. Both IRMCF312 and IRMCK312 come in the same 100-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production
Figure 1. Typical Application Block Diagram Using IRMCK312
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IRMCK312 2 IRMCK312 Block Diagram and Main Functions
IRMCK312 block diagram is shown in Figure 2.
Figure 2. IRMCK312 Internal Block Diagram IRMCK312 contains the following functions for sensorless AC motor control applications: * Motion Control Engine (MCETM) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transition o Multiply-divide (signed and unsigned) o Divide (signed and unsigned)
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IRMCK312
o o o o o o o o o o o o * Adder Subtractor Comparator Counter Accumulator Switch Shift ATAN (arc tangent) Function block (any curve fitting, nonlinear function) 16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) MCETM program and data memory (6K byte). Note 1 MCETM control sequencer
8051 microcontroller o Three 16-bit timer/counters o 16-bit periodic timer o 16-bit analog watchdog timer o 16-bit capture timer o Up to 36 discrete I/Os o Eleven-channel 12-bit A/D Five buffered channels (0 - 1.2V input) Six unbuffered channels (0 - 1.2V input) o JTAG port (4 pins) o Up to three channels of analog output (8-bit PWM) o Two UART o I2C/SPI port o 64K byte Note 1program One-Time Programmable memory o 2K byte data RAM. Note 2 Note 1: Total size of OTP memory is 64K byte, however MCE program occupies maximum 8K byte which will be loaded into internal RAM at a powerup/boot process. Therefore only 56K byte OTP memory area is usable for 8051 microcontroller. Note 2: Total size of RAM is 8K byte including MCE program, MCE data, and 8051 data. Different sizes can be allocated depending on applications.
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IRMCK312 3 Pinout
SCL/SO-SI/VPP P3.1/AOPWM2 P5.0/PFCGKILL 75 74 73 72 71 70 69 68 67
P3.6/RXD1
P3.7/TXD1
P3.3/INT1
P4.6/INT9
P5.2/TDO
P5.1/TMS
PLLVDD
PLLVSS
P5.3/TDI
P4.2/INT5
SDA/CS0
P3.5/T1
TCLK
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 XTAL0 XTAL1 P1.0/T2 P1.1/RXD P1.2/TXD P1.3/SYNC/SCK P1.4/CAP P1.5 P1.6 P1.7 P4.3/INT6 P4.7/INT10 VDD2 VSS VDD1 FGATEKILL FPWMWL FPWMWH FPWMVL FPWMVH FPWMUL FPWMUH P2.0/NMI P2.1 P2.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IFBC+ IFBFO AIN0/VDCO CMEXT AVDD IFBCO VDC+ AREF AVSS IFBCVDCAIN1 P3.0/INT2/CS1 PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL GATEKILL VDD1 VSS VDD2 P4.1/INT4 P4.5/INT8 IPFCIPFC+ IPFCO VACO VACVAC+ AIN6 AIN5 AIN4 AIN3 AIN2 DNC
IRMCK312
(Top View)
VSS
P3.4/T0
VDD1
NC
P3.2/INT0
RESET
VSS
PFCPWM
VDD2
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4.0/INT3
P2.6/AOPWM0
P2.7/AOPWM1
P4.4/INT7
VSS
VDD2
VSS
VDD1
P2.3
P2.4
P2.5
IFBF-
Figure 3. IRMCK312 Pin Configuration Attention: Pin 51 must be left floating. Do not connect.
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IFBF+
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IRMCK312 4 Input/Output of IRMCK312
All I/O signals of IRMCK312 are shown in Figure 4. All I/O pins are 3.3V logic interface except A/D interface pins.
Crystal
XTAL0 XTAL1 P1.1/RXD P1.2/TXD P3.6/RXD1 P3.7/TXD1 SDA SCL CPWMUH CPWMUL CPWMVH CPWMVL CPWMWH CPWMWL CGATEKILL FPWMUH FPWMUL FPWMVH FPWMVL FPWMWH FPWMWL FGATEKILL PFCPWM P5.0/PGKILL
Communication Interface
Channel 1 PWM gate signal Interface
P1.3/SYNC P1.4/CAP P3.0/INT2 P1.0/T2 P1.5 P1.6 P1.7 P2.0/NMI P2.1 P2.2 P2.3 P2.4 P2.5 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P4.0/INT3 P4.1/INT4 P4.2/INT5 P4.3/INT6 P4.4/INT7 P4.5/INT8 P4.6/INT9 P4.7/INT10
Channel 2 PWM gate signal Interface
Power Factor Control PWM gate signal Interface Analog Power
Discrete I/O
AVDD (1.8V) AVSS CMEXT AREF IFBC+ IFBCIFBCO IFBF+ IFBFIFBFCO VAC+ VACVACO IPFC+ IPFCIPFCO VDC+ VDCVDCO AIN1 AIN2 AIN3 AIN4 AIN5 AIN6
A/D Interface
D/A Interface (PWM output)
P2.6/AOPWM0 P2.7/AOPWM1 P3.1/AOPWM2 P5.3/TDI
JTAG port System Reset
TCLK P5.1/TSM P5.2/TDO RESET
Digital power/ ground PLL power/ ground
VPP(6.75V) VDD1(3.3V) VDD2(1.8V) VSS PLLVDD(1.8V) PLLVSS
Figure 4. Input/Output of IRMCK312
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IRMCK312
4.1 8051 Peripheral Interface Group
Input, Receive data to IRMCK312, can be configured as P1.1 Output, Transmit data from IRMCK312, can be configured as P1.2 Input, 2nd channel Receive data to IRMCK312, can be configured as P3.6 Output, 2nd channel Transmit data from IRMCK312, can be configured as P3.7
UART Interface P1.1/RXD P1.2/TXD P3.6/RXD1 P3.7/TXD1
Discrete I/O Interface P1.0/T2 Input/output port 1.0, can be configured as Timer/Counter 2 input P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock P1.4/CAP Input/output port 1.4, can be configured as Capture Timer input P1.5 Input/output port 1.5 P1.6 Input/output port 1.6 P1.7 Input/output port 1.7 P2.0/NMI Input/output port 2.0, can be configured as non-maskable interrupt P2.1 Input/output port 2.1 P2.2 Input/output port 2.2 P2.3 Input/output port 2.3 P2.4 Input/output port 2.4 P2.5 Input/output port 2.5 P3.0/INT2/CS1 Input/output port 3.0, can be configured as external interrupt 2 or SPI chip select 1 P3.2/INT0 Input/output port 3.2, can be configured as external interrupt 0 P3.3/INT1 Input/output port 3.3, can be configured as external interrupt 1 P3.4/T0 Input/output port 3.4, can be configured as Timer/Counter 0 input P3.5/T1 Input/output port 3.5, can be configured as Timer/Counter 1 input P4.0/INT3 Input/output port 4.0, can be configured as external interrupt 3 P4.1/INT4 Input/output port 4.1, can be configured as external interrupt 4 P4.2/INT5 Input/output port 4.2, can be configured as external interrupt 5 P4.3/INT6 Input/output port 4.3, can be configured as external interrupt 6 P4.4/INT7 Input/output port 4.4, can be configured as external interrupt 7 P4.5/INT8 Input/output port 4.5, can be configured as external interrupt 8 P4.6/INT9 Input/output port 4.6, can be configured as external interrupt 9 P4.7/INT10 Input/output port 4.7, can be configured as external interrupt 10 P5.0/PFCGKILL Input/output port 5.0, can be configured as PFCGKILL P5.1/TMS Input/output port 5.1, can be configured as JTAG TMS pin P5.2/TDO Input/output port 5.2, can be configured as JTAG TDO pin P5.3/TDI Input/output port 5.3, can be configured as JTAG TDI pin Analog Output Interface P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier frequency P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency
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IRMCK312
Crystal Interface XTAL0 XTAL1 Reset Interface RESET Input, connected to crystal Output, connected to crystal Inout, system reset, needs to be pulled up to VDD1 but doesn't require external RC time constant
I2C/SPI Interface SCL/SO-SI/VPP Output, I2C clock output, SPI SO-SI SDA/CS0 Input/output, I2C Data line, Chip Select 0 of SPI P3.0/INT2/CS1 Input/output port 3.0, can be configured as external interrupt 2 or SPI chip select 1 P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock
4.2
Motion Peripheral Interface Group
Output, motor 1 PWM phase U high side gate signal Output, motor 1 PWM phase U low side gate signal Output, motor 1 PWM phase V high side gate signal Output, motor 1 PWM phase V low side gate signal Output, motor 1 PWM phase W high side gate signal Output, motor 1 PWM phase W low side gate signal Output, motor 2 PWM phase U high side gate signal Output, motor 2 PWM phase U low side gate signal Output, motor 2 PWM phase V high side gate signal Output, motor 2 PWM phase V low side gate signal Output, motor 2 PWM phase W high side gate signal Output, motor 2 PWM phase W low side gate signal Output, PFC PWM Input, upon assertion, this negates all six PWM signals for motor 1, programmable logic sense Input, upon assertion, this negates PFCPWM signal, programmable logic sense, can be configured as discrete I/O in which case CGATEKILL negates PFCPWM Input, upon assertion, this negates all six PWM signals for motor 2, programmable logic sense
PWM CPWMUH CPWMUL CPWMVH CPWMVL CPWMWH CPWMWL FPWMUH FPWMUL FPWMVH FPWMVL FPWMWH FPWMWL PFCPWM Fault CGATEKILL P5.0/PFCGKILL FGATEKILL
4.3
Analog Interface Group
Analog power (1.8V) Analog power return Buffered 0.6V output Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected.
AVDD AVSS AREF CMEXT
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IRMCK312
IFBC+ IFBCIFBCO IFBF+ IFBFIFBFO IPFC+ IPFCIPFO VAC+ VACVACO VDC+ VDCAIN0/VDCO AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 Input, Operational amplifier positive input for shunt resistor current sensing of motor 1 Input, Operational amplifier negative input for shunt resistor current sensing of motor 1 Output, Operational amplifier output for shunt resistor current sensing of motor 1 Input, Operational amplifier positive input for shunt resistor current sensing of motor 2 Input, Operational amplifier negative input for shunt resistor current sensing of motor 2 Output, Operational amplifier output for shunt resistor current sensing of motor 2 Input, Operational amplifier positive input for PFC current sensing Input, Operational amplifier negative input for PFC current sensing Output, Operational amplifier output for PFC current sensing Input, Operational amplifier positive input for PFC AC voltage sensing Input, Operational amplifier negative input for PFC AC voltage sensing Output, Operational amplifier output for PFC AC voltage sensing Input, Operational amplifier positive input for DC bus voltage sensing Input, Operational amplifier negative input for DC bus voltage sensing Input/Output, Analog input channel 0 or Operational amplifier output for DC bus voltage sensing Input, Analog input channel 1 (0-1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 2 (0-1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 3 (0-1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 4 (0-1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 5 (0-1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 6 (0-1.2V), needs to be pulled down to AVSS if unused
4.4
Power Interface Group
Digital power for I/O (3.3V) Digital power for core logic (1.8V) Digital common PLL power (1.8V) PLL ground return OTP programming supply. Can be left open in OTP read mode (normal)
VDD1 VDD2 VSS PLLVDD PLLVSS SCL/SO-SI/VPP
4.5
Test Interface
Input, JTAG test data input Input, JTAG test mode select Input, JTAG test clock Output, JTAG test data output
P5.3/TDI P5.1/TMS TCK P5.2/TDO
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IRMCK312 5 Application Connections
Typical application connection is shown in Figure 5. All components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCK312.
System Clock
4MHz Crystal
XTAL0 XTAL1 PLLVDD 1.8V PLLVSS
PLL Logic RS232C RS232C I2C/SPI
System clock
To indoor unit Microcontroller (RS232C) To other Host (RS232C) Other Communication (I2C or SPI)
P1.2/TXD P1.1/RXD P3.7/TXD P3.6/RXD SDA/CS0 SCL/SO-SI/VPP P1.0/T2 P1.3/SYNC/SCK P1.4/CAP P1.5 P1.6 P1.7 P2.0/NMI P2.1 P2.2
Motion Control Modules Dual Port Memory (0.5kB) & MCE Memory (5.5kB)
Low Loss Space Vector PWM Low Loss Space Vector PWM
CPWMUH CPWMUL CPWMVH CPWMVL CPWMWH CPWMWL CGATEKILL FPWMUH FPWMUL FPWMVH FPWMVL FPWMWH FPWMWL FGATEKILL
PORT1
Motion Control Sequencer S/H
PFC PWM
PFCPWM PGATEKILL 0.6V IFBC+ IFBCIFBCO IFBF+ 0.6V FAN motor DC bus shunt resistor 0.6V FAN motor DC bus shunt resistor Compressor DC bus shunt resistor
Digital I/O Control
P2.3 P2.4 P2.5 P3.0/INT2/CS1 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P4.0/INT3 P4.1/INT4 P4.2/INT5 P4.3/INT6 P4.4/INT7 P4.5/INT8 P4.6/INT9 P4.7/INT10 P2.6/AOPWM0
PORT2
PORT3
Timers Watchdog Timer
S/H
IFBFIFBFO IPFC+
S/H
IPFCIPFCO
PORT4 Local RAM 2kByte 12bit A/D & MUX
VAC+ VACVACOMP VDC+ VDCOther Buffered Analog input AC line voltage
PWM0 PWM1 PWM2
P2.7/AOPWM1
Analog Output
P3.1/AOPWM2
Program OTP ROM (64kB)
VDCO 6 AIN1 - AIN6 AREF
Other analog input (0-1.2V) Optional External Voltage Reference (0.6V)
TCLK
JTAG Control
P5.3/TDI P5.1/TSM P5.2/TDO RESET SCL/SO-SI/VPP VDD1 VDD2 VSS
JTAG Port Interface 5 RESET
System Reset
System clock
CMEXT
8051 CPU
Clock divider
AVDD AVSS
1.8V
6.75V
Power
3.3V 1.8V
Figure 5. Application Connection of IRMCK312
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IRMCK312 6 DC Characteristics
6.1 Absolute Maximum Ratings
Parameter Min Typ Max Condition
Respect to VSS Respect to VSS Respect to VSS Respect to AVSS Respect to VSS Supply Voltage -0.3 V 3.6 V Supply Voltage -0.3 V 1.98 V OTP Programming -0.3V 7.0V Voltage Analog Input Voltage -0.3 V 1.98 V Digital Input Voltage -0.3 V 3.65 V Ambient Temperature -40 C 85 C Storage Temperature -65 C 150 C Table 1. Absolute Maximum Ratings
Symbol
VDD1 VDD2 VPP VIA VID TA TS
Caution: Stresses beyond those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied.
6.2
System Clock Frequency and Power Consumption
Parameter Min Typ Max Unit
MHz MHz System Clock 32 128 8051 Clock 32 Table 2. System Clock Frequency
Power Consumption
180 160 140 120 Power (mW) 100 80 60 40 20 0 0 20 40 60 80 100 120 140 MCE Frequency (MHz) 1.8V 3.3V Total Power
Symbol
SYSCLK 8051CLK
Figure 6. Clock Frequency vs. Power Consumption
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IRMCK312
6.3
VDD1 VDD2 VPP VIL VIH CIN IL IOL1(2) IOH1(2) IOL2(3) IOH2(3)
Digital I/O DC Characteristics
Parameter Min Typ Max Condition
Recommended Recommended Recommended Recommended Recommended
(1)
Symbol
Supply Voltage 3.0 V 3.3 V 3.6 V Supply Voltage 1.62 V 1.8 V 1.98 V OTP Programming 6.50V 6.75V 7.0V voltage Input Low Voltage -0.3 V 0.8 V Input High Voltage 2.0 V 3.6 V Input capacitance 3.6 pF Input leakage current 10 nA 1 A Low level output 8.9 mA 13.2 mA 15.2 mA current High level output 12.4 mA 24.8 mA 38 mA current Low level output 17.9 mA 26.3 mA 33.4 mA current High level output 24.6 mA 49.5 mA 81 mA current Table 3. Digital I/O DC Characteristics
(1)
VO = 3.3 V or 0 V VOL = 0.4 V = 2.4 V = 0.4 V = 2.4 V
VOH (1) VOL (1) VOH (1)
Note: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to P1.0/T2, P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P1.5, P1.6, P1.7, P2.0/NMI, P2.1, P2.2, P2.3, P2.4, P2.5, P2.6/AOPWM0, P2.7/AOPWM1, P3.0/INT2/CS1, P3.1/AOPWM2, P3.2/INT0, P3.3/INT1, P3.4/T0, P3.5/T1, P3.6/RXD1, P3.7/TXD1, P4.0/INT3, P4.1/INT4, P4.2/INT5, P4.3/INT6, P4.4/INT7, P4.5/INT8, P4.6/INT9, P4.7/INT10, P5.0/PFCGKILL, P5.1/TMS, P5.2/TDO, P5.3/TDI, CGATEKILL, FGATEKILL, CPWMUL, CPWMUH, CPWMVL, CPWMVH, CPWMWL, CPWMWH, FPWMUL, FPWMUH, FPWMVL, FPWMVH, FPWMWL, FPWMWH, and PFCPWM pins.
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6.4
VPLLVDD VIL OSC VIH OSC
PLL and Oscillator DC Characteristics
Parameter
Supply Voltage Oscillator Input Low Voltage Oscillator Input High Voltage Table 4.
Symbol
Min
1.62 V VPLLVSS
Typ
1.8 V -
Max
1.92 V 0.2* VPLLVDD VPLLVDD
(1)
Condition
Recommended VPLLVDD = 1.8 V VPLLVDD (1) = 1.8 V
0.8* VPLLVDD PLL DC Characteristics
Note: (1) Data guaranteed by design.
6.5
Analog I/O DC Characteristics
- OP amps for current sensing (IFBC+, IFBC-, IFBCO, IFBF+, IFBF-, IFBFO, IPFC+, IPFC-, IPFCO) CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25C.
Symbol
VAVDD VOFFSET VI VOUTSW CIN RFDBK
Parameter
Supply Voltage Input Offset Voltage Input Voltage Range OP amp output operating range Input capacitance OP amp feedback resistor
Min
1.71 V 0V 50 mV
(1)
Typ
1.8 V 3.6 pF -
Max
1.89 V 26 mV 1.2 V 1.2 V 20 k
Condition
Recommended VAVDD = 1.8 V Recommended VAVDD = 1.8 V
(1)
5 k
Requested between op amp output and negative input
(1) (1)
Operating Close loop 80 db Gain CMRR Common Mode 80 db Rejection Ratio ISRC Op amp output 1 mA source current ISNK Op amp output sink 100 A current Table 5. Analog I/O DC Characteristics Note: (1) Data guaranteed by design.
OP GAINCL
VOUT (1) VOUT (1)
= 0.6 V = 0.6 V
Rev 1.0
6.6
Under Voltage Lockout DC Characteristics
- Based on AVDD (1.8V) Unless specified, Ta = 25C.
Symbol
UVCC+ UVCCUVCCH
Parameter
Min
Typ
Max
Condition
VDD1 = 3.3 V VDD1 = 3.3 V
UVcc positive going 1.53 V 1.66 V 1.71 V Threshold1) UVcc negative going 1.52 V 1.62 V 1.71 V Threshold UVcc Hysteresys 40 mV Table 6. UVcc DC Characteristics
Note: 1) Data guaranteed by design.
6.7
AREF Characteristics
Parameter Min Typ Max
(1)
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25C.
Symbol
VAREF Vo PSRR
Condition
VAVDD (1) = 1.8 V
AREF Output Voltage 495 mV 600 mV 700 mV Load regulation (VDC-0.6) 1 mV Power Supply Rejection 75 db Ratio Table 7. AREF DC Characteristics
Note: (1) Data guaranteed by design.
Rev 1.0
IRMCK312 7 AC Characteristics
7.1
FCLKIN FPLL FLWPW JS D TLOCK
PLL AC Characteristics
Parameter Min Typ Max
(1) (1)
Symbol
Condition
(see figure below)
Crystal input 3.2 MHz 4 MHz 60 MHz frequency Internal clock 32 MHz 50 MHz 128 MHz frequency Sleep mode output FCLKIN / 256 frequency Short time jitter 200 psec Duty cycle 50 % PLL lock time 500 sec Table 8. PLL AC Characteristics
(1)
(1) (1) (1)
Note: (1) Data guaranteed by design.
R1=1M
R2=10
Xtal
C1=30PF C2=30PF
Figure 7 Crystal oscillator circuit
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IRMCK312
7.2 Analog to Digital Converter AC Characteristics
Parameter
Conversion time Sample/Hold maximum hold time
Unless specified, Ta = 25C.
Symbol
TCONV THOLD
Min
-
Typ
-
Max
2.05 sec 10 sec
(1)
Condition
Voltage droop 15 LSB (see figure below)
Table 9. A/D Converter AC Characteristics Note: (1) Data guaranteed by design.
Input Voltage Voltage droop S/H Voltage
tSAMPLE THOLD
Figure 8 Voltage droop of sample and hold
7.3
Op Amp AC Characteristics
- OP amps for current sensing (IFBC+, IFBC-, IFBCO, IFBF+, IFBF-, IFBFO, IPFC+, IPFC-, IPFCO) Unless specified, Ta = 25C.
Symbol
OPSR OPIMP TSET
Parameter
OP amp slew rate OP input impedance Settling time
Min
-
Typ
10 V/sec 108 400 ns
Max
(1)
Condition
VAVDD = 1.8 V, CL = 33 pF (1)
VAVDD = 1.8 V, CL = 33 pF (1) Table 10. Current Sensing OP Amp AC Characteristics
Note: (1) Data guaranteed by design.
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IRMCK312
7.4 SYNC to SVPWM and A/D Conversion AC Timing
twSYNC
SYNC
tdSYNC1
IU,IV,IW
tdSYNC2
AINx
tdSYNC3
PWMUx,PWMVx,PWMWx
Figure 9 SYNC to SVPWM and A/D conversion AC Timing Unless specified, Ta = 25C.
Symbol
twSYNC tdSYNC1 tdSYNC2 tdSYNC3
Parameter
Min
Typ
Max
Unit
SYSCLK SYSCLK SYSCLK
(1)
SYNC pulse width 32 100 SYNC to current feedback conversion time 200 SYNC to AIN0-6 analog input conversion time SYNC to PWM output 2 delay time Table 11. SYNC AC Characteristics
SYSCLK
Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events
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IRMCK312
7.5 GATEKILL to SVPWM AC Timing
Figure 10 GATEKILL to SVPWM AC Timing Unless specified, Ta = 25C.
Symbol
twGK tdGK
Parameter
Min
Typ
Max
Unit
SYSCLK SYSCLK
GATEKILL pulse width 32 GATEKILL to PWM 100 output delay Table 12. GATEKILL to SVPWM AC Timing
7.6
Interrupt AC Timing
Figure 11 Interrupt AC Timing Unless specified, Ta = 25C.
Symbol
twINT tdINT
Parameter
Min
Typ
Max
Unit
SYSCLK SYSCLK
INT0, INT1 Interrupt 4 Assertion Time INT0, INT1 latency 4 Table 13. Interrupt AC Timing
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IRMCK312
7.7 I2C AC Timing
TI2CLK TI2CLK
SCL tI2WSETUP tI2WHOLD tI2RSETUP tI2RHOLD tI2EN2
tI2ST1 tI2ST2
tI2EN1
SDA
Figure 12 I2C AC Timing Unless specified, Ta = 25C.
Symbol
TI2CLK tI2ST1 tI2ST2 tI2WSETUP tI2WHOLD tI2RSETUP tI2RHOLD
2
Parameter
I C clock period I2C SDA start time I2C SCL start time I2C write setup time I2C write hold time I2C read setup time I2C read hold time
Min
Typ
Max
8192 -
Unit
SYSCLK TI2CLK TI2CLK TI2CLK TI2CLK SYSCLK SYSCLK
10 0.25 0.25 0.25 0.25 I2C filter time(1) 1 Table 14. I2C AC Timing
Note: (1) I2C read setup time is determined by the programmable filter time applied to I2C communication.
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IRMCK312
7.8 SPI AC Timing
7.8.1 SPI Write AC timing
Figure 13 SPI AC Timing Unless specified, Ta = 25C.
Symbol
TSPICLK tSPICLKHT tSPICLKLT tCSDELAY tWRDELAY tCSHIGH tCSHOLD
Parameter
Min
Typ
Max
Unit
SYSCLK TSPICLK TSPICLK nsec nsec TSPICLK TSPICLK
SPI clock period 4 SPI clock high time 1/2 SPI clock low time 1/2 CS to data delay time 10 CLK falling edge to data 10 delay time CS high time between two 1 consecutive byte transfer CS hold time 1 Table 15. SPI Write AC Timing
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IRMCK312
7.8.2 SPI Read AC Timing
Figure 14 SPI Read AC Timing Unless specified, Ta = 25C.
Symbol
TSPICLK tSPICLKHT tSPICLKLT tCSRD tRDSU tRDHOLD tCSHIGH tCSHOLD
Parameter
Min
Typ
Max
Unit
SYSCLK TSPICLK TSPICLK nsec nsec nsec TSPICLK TSPICLK
SPI clock period 4 SPI clock high time 1/2 SPI clock low time 1/2 CS to data delay time 10 SPI read data setup time 10 SPI read data hold time 10 CS high time between two 1 consecutive byte transfer CS hold time 1 Table 16. SPI Read AC Timing
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IRMCK312
7.9 UART AC Timing
TBAUD
TXD
Start Bit
RXD
Data and Parity Bit
Stop Bit
TUARTFIL
Figure 15 UART AC Timing
Unless specified, Ta = 25C.
Symbol
TBAUD TUARTFIL
Parameter
Min
Typ
Max
-
Unit
bit/sec TBAUD
Baud Rate Period 57600 UART sampling filter 1/16 period (1) Table 17. UART AC Timing
Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated.
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IRMCK312
7.10 CAPTURE Input AC Timing
Figure 16 CAPTURE Input AC Timing Unless specified, Ta = 25C.
Symbol
TCAPCLK tCAPHIGH tCAPLOW tCRDELAY tCLDELAY tINTDELAY
Parameter
Min
Typ
Max
4 4 4
Unit
SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK
CAPTURE input period 8 CAPTURE input high 4 time CAPTURE input low 4 time CAPTURE falling edge to capture register latch time CAPTURE rising edge to capture register latch time CAPTURE input interrupt latency time Table 18. CAPTURE AC Timing
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(c) 2007 International Rectifier
IRMCK312
7.11 JTAG AC Timing
TJCLK
TCK
tJHIGH
tJLOW
tCO
TDO tJSETUP tJHOLD
TDI/TMS
Figure 17 JTAG AC Timing
Unless specified, Ta = 25C.
Symbol
TJCLK tJHIGH tJLOW tCO tJSETUP tJHOLD
Parameter
Min
Typ
Max
50 5 -
Unit
MHz nsec nsec nsec nsec nsec
TCK Period TCK High Period 10 TCK Low Period 10 TCK to TDO propagation 0 delay time TDI/TMS setup time 4 TDI/TMS hold time 0 Table 19. JTAG AC Timing
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IRMCK312
7.12 OTP Programming Timing
Figure 18 OTP Programming Timing Unless specified, Ta = 25C.
Symbol
TVPS TVPH
Parameter
Min
Typ
Max
Unit
nsec nsec
VPP Setup Time 10 VPP Hold Time 15 Table 20. OTP Programming Timing
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IRMCK312 8 I/O Structure
The following figure shows the motor PWM and digital I/O structure except the motor PWM output
Figure 19 All digital I/O except motor PWM output
The following figure shows RESET and GATEKILL I/O structure.
Figure 20 RESET, GATEKILL I/O
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(c) 2007 International Rectifier
IRMCK312
The following figure shows the analog input structure.
AVDD
Analog input
6.0V PIN 100 Analog Circuit
6.0V
AVSS
Figure 21 Analog input The following figure shows all analog operational amplifier output pins and AREF pin I/O structure.
1.8V
Analog output
6.0V PIN Analog Circuit
6.0V
AVSS
Figure 22 Analog operational amplifier output and AREF I/O structure The following figure shows the VPP pin I/O structure
Figure 23 VPP programming pin I/O structure
The following figure shows the VSS, AVSS and PLLVSS pin structure
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IRMCK312
Figure 24 VSS, AVSS and PLLVSS pin structure The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure
PIN
6.0V
VSS
Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure The following figure shows the XTAL0 and XTAL1 pins structure
Figure 26 XTAL0/XTAL1 pins structure
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(c) 2007 International Rectifier
IRMCK312 9 Pin List
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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Pin Name
XTAL0 XTAL1 P1.0/T2 P1.1/RXD P1.2/TXD P1.3/SYNC/ SCK P1.4/CAP P1.5 P1.6 P1.7 P4.3/INT6 P4.7/INT10 VDD2 VSS VDD1 FGATEKILL FPWMWL FPWMWH FPWMVL FPWMVH FPWMUL FPWMUH P2.0/NMI P2.1 P2.2 P2.3 P2.4 P2.5 P2.6/ AOPWM0 P2.7/ AOPWM1 VDD2
Internal IC Pin Pull-up Type /Pull-down
I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P P I 70 k Pull up 70 k Pull up 70 k Pull up 70 k Pull up 70 k Pull up 70 k Pull up O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O P
32
Description
Crystal input Crystal output Discrete programmable I/O or Timer/Counter 2 input Discrete programmable I/O or UART receive input Discrete programmable I/O or UART transmit output Discrete programmable I/O or SYNC output or SPI clock output Discrete programmable I/O or Capture Timer input Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O or Interrupt 6 Discrete programmable I/O or Interrupt 10 1.8V digital power Digital common 3.3V digital power Fan PWM shutdown input, 2-sec digital filter, configurable either high or low true. Fan PWM gate drive for phase W low side, configurable either high or low true Fan PWM gate drive for phase W high side, configurable either high or low true Fan PWM gate drive for phase V low side, configurable either high or low true Fan PWM gate drive for phase V high side, configurable either high or low true Fan PWM gate drive for phase U low side, configurable either high or low true Fan PWM gate drive for phase U high side, configurable either high or low true Discrete programmable I/O or Non Maskable Interrupt Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O or analog output 0 (PWM) Discrete programmable I/O or analog output 1 (PWM) 1.8V digital power
(c) 2007 International Rectifier
IRMCK312
Pin Number
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
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Pin Name
VSS VSS VDD1 P4.0/INT3 P4.4/INT7 IFBFIFBF+ IFBFO AIN0/VDCO VDC+ VDCAVDD AVSS AIN1 CMEXT AREF IFBCIFBC+ IFBCO DNC AIN2 AIN3 AIN4 AIN5 AIN6 VAC+ VACVACO IPFCO IPFC+ IPFCP4.5/INT8 P4.1/INT4 VDD2
Internal IC Pin Pull-up Type /Pull-down
P P P I/O I/O I I O O I I P P I O O I I O I I I I I I I O O I I I/O I/O P
Description
Digital common Digital common 3.3 V digital power Discrete programmable I/O or Interrupt 3 Discrete programmable I/O or Interrupt 7 Fan single shunt current sensing OP amp input (-) Fan single shunt current sensing OP amp input (+) Fan single shunt current sensing OP amp output Analog input channel 0 or DC bus voltage sensing OP amp output DC bus voltage sensing OP amp input (+) DC bus voltage sensing OP amp input (-) Analog power (1.8V) Analog common Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused Unbuffered analog reference voltage output (0.6V) Analog reference voltage output (0.6V) Compressor single shunt current sensing OP amp input (-) Compressor single shunt current sensing OP amp input (+) Compressor single shunt current sensing OP amp output Do not connect. Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused AC input voltage sensing OP amp input (+) AC input voltage sensing OP amp input (-) AC input voltage sensing OP amp output PFC shunt current sensing OP amp output PFC shunt current sensing OP amp input (+) PFC shunt current sensing OP amp input (-) Discrete programmable I/O or Interrupt 8 Discrete programmable I/O or Interrupt 4 1.8 V digital power
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IRMCK312
Pin Number
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
Pin Name
VSS VDD1 CGATEKILL CPWMWL CPWMWH CPWMVL CPWMVH CPWMUL CPWMUH P3.0/INT2/ CS1 P5.0/ PFCGKILL PFCPWM P3.1/ AOPWM2 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/RXD1 P3.7/TXD1 VSS VSS VDD1 P4.2/INT5 P4.6/INT9 SCL/SOSI/VPP SDA/CS0 P5.1/TMS P5.2/TDO
Internal IC Pin Pull-up Type /Pull-down
P P I 70 k Pull up 70 k Pull up 70 k Pull up 70 k Pull up 70 k Pull up 70 k Pull up O O O O O O I/O I 70 k Pull up O I/O I/O I/O I/O I/O I/O I/O P P P I/O I/O I/O I/O I/O I/O
Description
Digital common 3.3V digital power Compressor PWM shutdown input, 2-sec digital filter, configurable either high or low true. Compressor PWM gate drive for phase W low side, configurable either high or low true Compressor PWM gate drive for phase W high side, configurable either high or low true Compressor PWM gate drive for phase V low side, configurable either high or low true Compressor PWM gate drive for phase V high side, configurable either high or low true Compressor PWM gate drive for phase U low side, configurable either high or low true Compressor PWM gate drive for phase U high side, configurable either high or low true Discrete programmable I/O or INT2 digital input or SPI Chip Select 1 Discrete programmable I/O or PFC PWM shutdown input, 2-sec digital filter, configurable either high or low true. PFC PWM gate drive, configurable either high or low true Discrete programmable I/O or analog output 2 (PWM) Discrete programmable I/O or external interrupt 0 Discrete programmable I/O or external interrupt 1 Discrete programmable I/O or Timer/Counter 0 input Discrete programmable I/O or Timer/Counter 1 input Discrete programmable I/O or 2nd UART receive input Discrete programmable I/O or 2nd UART transmit output Digital common Digital common 3.3V digital power Discrete programmable I/O or Interrupt 5 Discrete programmable I/O or Interrupt 9 I2C clock output or SPI data or OTP power supply during programming I2C data or SPI Chip Select 0 Discrete programmable I/O or JTAG test mode select Discrete programmable I/O or JTAG port test data output
34 (c) 2007 International Rectifier
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IRMCK312
Pin Number
94 95 96 97 98 99 100
Pin Name
P5.3/TDI TCK TSTMOD RESET VDD2 PLLVDD PLLVSS
Internal IC Pin Pull-up Type /Pull-down
58 k pull down I/O I I
Description
Discrete programmable I/O or JTAG test data input JTAG test clock Test mode. Must be tied to VSS. Factory use only
I/O Reset, low true, Schmitt trigger input P 1.8V digital power P 1.8V PLL power. P PLL ground. Table 21. Pin List
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(c) 2007 International Rectifier
IRMCK312 10 Package Dimensions
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IRMCK312 11 Part Marking Information
12 Ordering Information
Lead-Free Part in 100-lead QFP Moisture sensitivity rating - MSL3 Part number IRMCK312TR Order quantities 1000 parts on tape and reel in dry pack
The LQFP-100 is MSL3 qualified This product has been designed and qualified for the industrial level Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/25/2007
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(c) 2007 International Rectifier

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